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PoroCYon
Posted on 12-01-19 12:59 PM, in GBAtek addendum/errata (rev. 5 of 11-16-20 05:38 PM) Link | #1406
Some that need to be confirmed:

DSP

  • DSP_PSTS bits 10..12 (REP0..REP2) are active-high (as in, 1=was written by DSP), while GBAtek says they're active-low

  • DSP_PCFG bits 12..15 have an undocumented transer mode (7: ARM9 bus loopback): transfers to/from the ARM9 bus, cf. DSP-internal DMA transfer mode 7. This mode requres some additional setup: you first need to set the following DSP-internal DMA registers to the following values (using transfer mode 1):

    [0x81BE] = 0 // select channel 0
    [0x81C6] = 0xABCD // destination address, high 16-bit
    [0x80E2] = 0 | (0<<1) | (1<<4) // configure AHBM (DSP->ARM9 DMA) // example value works for 16-bit transfers (see GBATek/Teakra docs for details)
    [0x80E4] = (1<<9) | 1<<8) // resp. mandatory bit, direction (0=read, 1=write) (see GBATek/Teakra docs for details)
    [0x80E6] = 1 // enable channel 0

    Then perform a transfer as follows (the example writes 0x1337 to 0xABCDEF98):

    DSP_PADR = 0xEF98 // destination address, low 16-bit
    DSP_PDATA = 0x1337 // for a write, read from this address for a read

PoroCYon
Posted on 12-09-19 08:04 PM, in How to run Melon DS on Ubuntu? Link | #1413
sudo apt-get install libsdl2 (or maybe 'libsdl2-2.0-0' instead of 'libsdl2')

PoroCYon
Posted on 09-28-20 09:10 AM, in Melonds not working since the update on linux Link | #2451
Try running "ldd path/to/melonDS", melonDS switched from pcap to slirp, ldd might tell you you're missing the libslirp libraries.

Or you can try installig libslirp and see if that worked.

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PoroCYon
Posted on 10-24-20 02:56 PM, in Framerate dropping while recording Link | #2618
that or, if you're lucky, it's only your OS scheduler messing things up. you could try upping the priority of the melonDS process, and try switching to a less CPU-intensive encoder on the OBS side

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PoroCYon
Posted on 10-24-20 04:29 PM, in Framerate dropping while recording Link | #2622
Posted by Generic aka RSDuck
it's just that the Windows scheduler gives defocused graphical applications less cpu time, because if you don't focus them, you probably aren't interested in seeing what's happening in them at fullspeed.


either that, or the "window idle" event firing less often for the same reason (if that's being used to run a main loop iteration, but I'm not sure about the latter)

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PoroCYon
Posted on 11-16-20 05:05 PM, in If you'd like to translate melonDS: read this post Link | #2758
I can do Dutch (and Lojban), and you know the answer to the other questions I think.

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PoroCYon
Posted on 11-16-20 05:10 PM, in How do you run? Link | #2760
Which Qt version do you have installed? Which distro + version are you running?

Because to me this sounds a lot like https://github.com/Arisotura/melonDS/issues/751 .

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PoroCYon
Posted on 11-16-20 05:30 PM, in GBAtek addendum/errata (rev. 7 of 11-16-20 06:40 PM) Link | #2762

IR cartridges

IR cartridges seem to work as follows, but I'd like to have someone else to verify this (seems to work with HGSS, BW and B2W2 carts, idk about others):

Everything automatically happens at 115200 baud, 8n1.

There seem to be three main SPI commands that are sent to what normally would be the savegame SPI bus, there's a fourth command to perform actual savegame operations. All transfers happen at 1 MHz (serial AUXSPI mode) unless indicated otherwise.

The cartridge needs to be powered on, but nothing more besides this. No header reading or KEY1/KEY2 init, and so on. (I rebooted the cart with SCFG_MC and started doing SPI commands immediately afterwards, seems to work fine).

The commands:
  • 0x00: savegame escape byte: as long as chip select is held, the bytes that follow will be treated like a regular savegame transfer. These can also happen at any clock speed, but the 0x00 byte itself needs to be transferred at 1 MHz. (This bit was already known.)
  • 0x01: receive data from IR: one command byte (0x01) is written, after which data bytes are read by the DS. The first byte read indicates the amount of bytes that will follow. It doesn't seem to be able to receive more than 255 bytes afaics. Bytes written to perform the reads are unused as far as I know, but usually set to 0 (HGSS does this, at least).
    • When there are zero bytes to read, you still have to deselect the SPI chip, or the next transfer will fail. Disable the 'chip select hold' bit in AUXSPICNT and send a zero byte.
  • 0x02: send data over IR: this one has no length prefix, chip select is used to determine when the transfer ends, as usual.
  • 0x08: not too sure about this, but probably a status thing. A command byte (0x08) is sent, and a status byte(?) is received from the cart. HGSS seems to always send two of these one after another, carts seem to return 0x00 on the first one and 0xaa for the second, unless other IR devices are sending actively, then both bytes are 0xaa.
HGSS, while trying to connect to a Pokéwalker, seems to first do a cmd 0x01, which returns 0 bytes, then 0x08 twice, after which it repeatedly issues other 0x01 commands until the return data of one of these indicates a Pokéwalker presence (the Pokéwalker sends out a fixed byte value as 'beacon' thing, the game will receive a 1-byte packet containing that beacon). 0x08 is never used again after being used twice in the beginning as far as I can see (but I might be wrong).

Allegedly, the chip in carts responsible for IR is a H8/38606R (connected to the SPI bus on one side, and to some IR leds or so on the other), just like the one in the Pokéwalker. Getting its ROM dumped sounds like a fun challenge.

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Main - Posts by PoroCYon

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